cy22388, cy22389, cy22391 factory programmable quad pll clock generator with vcxo cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07734 rev. *c revised january 13, 2009 features fully integrated phase-locked loops (plls) qfn package 40% smaller than 20-pin tssop 22% smaller than 16-pin tssop selectable output frequency programmable output frequencies output frequency range of 5?166 mhz input frequency range crystal: 10?30 mhz external reference: 1?100 mhz analog vcxo 16-/20-pin tssop and 32-pin qfn packages 3.3v operation with 2.5v output buffer option benefits meets most digital set top box, dvd recorder, and dtv appli- cation requirements multiple high-performance plls allow synthesis of unrelated frequencies integration eliminates the need fo r external loop filter compo- nents meets critical timing requirem ents in complex system designs enables application compatibility complete vcxo solution with 120 ppm (typical pull range) pinouts figure 1. pin diagram - 16-pin tssop cy22388 vcxo clka xout xin dividers & multiplexers pll4 pll1 pll2 pll3 oe/pd# clkb clkc clkd clke clkf clkg clkh vin fs0 fs1 fs2 select logic (cy22389 & cy22391 only) (cy22389 & cy22391 only) (cy22389 & cy22391 only) (cy22389 & cy22391 only) logic block diagram cy22388 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 xin fs0 fs1 vin vdd vss clka clkb clkc clkd clke vss vdd fs2 vdd xout 16-pin tssop [+] feedback
cy22388, cy22 389, cy22391 document #: 38-07734 rev. *c page 2 of 10 cy22389 1 2 3 4 5 6 7 813 14 15 16 17 18 19 20 xin fs0 fs1 clkh vdd vss clkd clkb clkg vss vdd vin fs2 oe/pd# vdd xout clka clkf clkc clke 912 10 11 20- pin tssop 1 2 3 4 5 6 8 7 24 23 22 21 20 19 17 18 16 15 14 13 12 11 9 10 32 31 30 29 28 27 25 26 cy22391 vin vdd vdd vss vss vss vss clkh clkd clkb clka nc nc clkc clke vdd clkf clkg vss vss vdd vdd fs2 oe/pd# vdd vdd xout nc nc xin fs0 fs1 32-pin qfn figure 2. pin diagram - 20-pin tssop cy22389 figure 3. pin diagram - 32-pin tssop cy22391 pin definitions pin name pin number pin description 16-pin tssop 20-pin tssop 32-pin qfn xin 1 1 30 crystal input or reference clock input xout 16 20 27 crystal output (no connect if external clock is used) clka 7 9 11 clock output clkb 8 8 10 clock output clkc 9 10 14 clock output clkd 10 7 9 clock output clke 11 11 15 clock output clkf n/a 12 17 clock output clkg n/a 13 18 clock output clkh n/a 4 8 clock output fs0 2 2 31 frequency select 0 fs1 3 3 32 frequency select 1 fs2 14 17 23 frequency select 2 oe/pd# n/a 18 24 programmable control pin: output enable (active-high) or power down (active-low) vin 4 16 1 analog control input for vcxo vdd 5,13,15 5,15,19 2,3,16,21,22,25,26 voltage supply vss 6,12 6,14 4,5,6,7,19,20 ground nc n/a n/a 12,13,28,29 no connect. [+] feedback
cy22388, cy22 389, cy22391 document #: 38-07734 rev. *c page 3 of 10 general description the cy22388 family of devices has an analog vcxo (voltage controlled crystal oscillator), 4 plls, up to 8 clock outputs and frequency selection ca pabilities. the frequency selects do not modify any pll frequency. instead they allow the user to choose between up to 8 different output divider selections depending on the clock and package configuration. this is illustrated in the following frequency selection tables and functional block diagram. there is one programmable oe/pd#. the oe/pd# pin can be programmed as either an output enable pin or a power down pin. the oe function can be programmed to disable a selected set of outputs when low, leaving the remaining outputs running. full-chip power down disable all outputs and the plls and most of the active circuitry when low. factory-programmable cy22388/89/91 factory programming is available for high- or low-volume manufacturing by cypress. all re quests must be submitted to the local cypress field application engineer (fae) or sales repre- sentative. once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. this part number is used for additional sample requests and production orders. plls the advantage of having four plls is that a single device can generate up to four independent frequencies from a single crystal. generally a design may require up to four oscillators to accomplish what could be done with a single cy22388. each pll is independent and can be configured to generate a vco (voltage controlled oscillator) frequency between 62.5 mhz and 250 mhz. each pll can then in turn be divided down with post dividers to generate the clock output frequency of the user?s choice. the output divider allows each clock output to be divided by 1, 2, 3, 4, 5, 6, 8, 9, 10, 12 or 15. the pll maximum is reduced to 166 mhz in divide by 1 mode due to output buffer limitations. outputs that allow frequency switching perform the transition free of glitches. a glitch is defined as a high or low time shorter than half the smaller of the tw o periods being switched between. extended low time (even many cycles in duration) is acceptable. selected clock outputs are capable of being powered off a separate 2.5v supply. this allows for driving lower voltage swing inputs. the cy22388/89/91 device still requires 3.3v to power the oscillator and all other internal pll circuitry. for the 2.5v output option please refer to the cy22388 application note. selected clocks and pinout diagrams are explained in this appli- cation note. clock d can obtain its output from either the reference source or pll1/n1 with n1 being defined as the output divider for pll1. clock h is defined as a copy of clock d. clock d is only available from pll1/n1 on the 16-pin package. for cy22388, clkb and clkc have related frequencies. for cy22389 and cy22391, clkd and clkf have related frequencies, clka and clkb have related frequencies, and clkc and clke have related frequencies. related frequencies come from the same pll but can have different divider values. in order to minimize ppm (parts per million) error on the clock outputs, a user must choose a crystal reference frequency that is a common multiple of the desired pll frequencies. while this would be the ideal situation, this is not always the case and the plls have high-resolution counters internally to help minimize frequency deviation from the desired frequency. pll vco frequencies are generated by the following equation: f vco = f ref * (p / q) where f ref is the reference input frequency, p is the pll feedback divider and q is the reference input divider. a pll is a feedback system where the vco frequency divided by p and reference frequency divided by q are constantly being compared and the vco frequency is adjusted to achieve a locked state. figure 3 is a simplified drawing of a pll. figure 3. pll system frequency select pin operation table 1. cy22388 16-pin tssop output signal frequency selection lines clk a fs2, fs1, fs0 clk b fs1, fs0 clk c & clk d s0 clk e fixed table 2. cy22389 20-pin tssop output signal frequency selection lines clk a fs2, fs1, fs0 clk b & clk c fs1, fs0 clk d, clk e, & clk f fs0 clk g fixed clk h copy of clk d table 3. cy22391 32-pin qfn output signal frequency selection lines clk a fs2, fs1, fs0 clk b & clk c fs1, fs0 clk d, clk e, & clk f fs0 clk g fixed clk h copy of clk d f ref /q vc o and other co m pon ents /p f vco [+] feedback
cy22388, cy22 389, cy22391 document #: 38-07734 rev. *c page 4 of 10 analog vcxo there are three programmable reference operating modes for the cy22388, cy22389, cy22391 family of devices. the first mode utilizes an external pullable crystal and incorporates an internal analog vcxo. the second mode configures the internal crystal oscillator to accept an external driven refer ence source from 1 to 100 mhz. the input capacitance on the xin pin when driven in this mode is 15 pf. the third mode disables the vcxo input control and sets the internal oscillator to a fixed frequency operation. the load capac- itance seen by the external crystal when connected to pins xin and xout is equal to 12 pf. one of the key components to the cy22388, cy22389, cy22391 family of devices is the analog vcxo. the vcxo is used to ?pull? the reference crystal higher or lower in order to lock the system frequency to an external source. this is ideal for applications where the output frequency needs to track along with an external reference frequency that is constantly shifting. the vcxo is completely analog, so there is infinite resolution on the vcxo pull curve. the analog to digital converter steps that are normally associated with a digi tal vcxo input is not present in this device. a special pullable crystal must be used to in order to have adequate vcxo pull ran ge. pullable crystal specifica- tions are included in this data sheet. please refer to the cy22388, cy22389, cy22391 application note for pullable crystal recommendations outside of the standard industry frequencies given in the pullable crystal specifications. vcxo profile figure 4 shows an example of what a vcxo profile looks like. the analog voltage input is on the x-axis and the ppm range is on the y-axis. an increase in the vcxo input voltage results in a corresponding increase in the output frequency. this has the effect of moving the ppm from a negative to positive offset. figure 4. vcxo profile -200 -150 -100 -50 0 50 100 150 200 00.511.5 22.533.5 vcxo input [v] tuning [pp m absolute maximum conditions parameter description condition min max unit v dd /av dd /v ddl core supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non-functional ?65 +125 c esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? volts ul-94 flammability rating v-0 at 1/8 in. ? 10 ppm msl moisture sensitivity level qfn package 3 16- and 20-pin tssop 1 pullable crystal specifications [1, 3] parameter description comments min typ. max unit f nom 13.5 mhz and 27 mhz crystal at-cut parallel resonance, fundamental mode see note 3 c lnom nominal load capacitance order crystal at one specific c lnom 0 ppm 11.4 12 12.6 pf r 1 equivalent series resistance (esr) fundamental mode (cl = series) ? ? 40 dl crystal drive level nominal vdd at 25c over 120 ppm pull range ? ? 300 w c 0 [2] crystal shunt capacitance 1.5 3 4.0 pf notes 1. device operates to the following specs, which are guaranteed by design. 2. increased tolerance available fr om pull range less than 120ppm. 3. refer to cy22388 application note and online software for a list of approved crystal specifications. [+] feedback
cy22388, cy22 389, cy22391 document #: 38-07734 rev. *c page 5 of 10 c 1 [2] crystal motional capacitance 12 14 16.8 ff f 3sephi [3] third overtone separation from 3*f nom mechanical third (high side of 3*f nom ) 240 ? ? ppm f 3seplo [3] third overtone separation from 3*f nom mechanical third (low side of 3*f nom ) ? ? ?120 ppm recommended oper ating conditions parameter description min typ. max unit v dd /av dd /v ddl operating voltage 3.0 3.3 3.6 v t a ambient temperature ?10 ? 70 c c load maximum load capacitance ? ? 15 pf t pu power up time for all v dd s reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms dc parameters [4] parameter description conditions min typ. max unit i oh [5] output high current v oh = v dd ? 0.5, v dd = 3.3v 12 ? ? ma i ol [5] output low current v ol = 0.5, v dd = 3.3v 12 ? ? ma i ih input high current v ih = v dd , excluding vin, xin ? 5 10 a i il input low current v il = 0v, excluding vin, xin ? 5 10 a v ih input high voltage fs0/1/2 oe input cmos levels 0.7xa vdd ?? v v il input low voltage fs0/1/2 oe input cmos levels ? ? 0.3xa vdd v parameter description conditions min typ. max unit v vcxo vin input range 0 ? a vdd v c in input capacitance fs0/1/2 and oe pins only ? ? 7 pf i vdd supply current v dd /av dd /v ddl current ?60?ma c inxin input capacitance at xin vcxo disabled external reference ? 15 ? pf c inxtal input capacitance at crystal vcxo disabled fixed freq. oscillator ? 12 ? pf ac parameters parameter [4] description conditions min typ. max units 1/t1 output frequency pll minmax /divider maximum 4.2 ? 166 mhz dc1 output duty cycle (excluding refout ) duty cycle is defined in figure 6 ; t 2 /t 1 , 50% of v dd external reference duty cycle between 40% and 60% measured at v dd /2 (clock output is 125 mhz) 45 50 55 % dc2 output duty cycle duty cycle is defined in figure 6 ; t 2 /t 1 , 50% of v dd external reference duty cycle between 40% and 60% measured at v dd /2 (clock output is > 125 mhz) 40 50 60 % dc refout output duty cycle duty cycle is defined in figure 6 ; t 2 /t 1 , 50% of v dd (xin duty cycle = 45/55%) 40 50 60 % pullable crystal specifications [1, 3] parameter description comments min typ. max unit notes 4. parameters are guaranteed by design and characterization. not 100% tested in production. all parameters specified with fully loaded outputs. 5. custom drive level and is available upon request [+] feedback
cy22388, cy22 389, cy22391 document #: 38-07734 rev. *c page 6 of 10 figure 5. test and measurement voltage and timing definitions figure 6. duty cycle definition figure 7. er = (0.6 v dd )/t 3 , ef = (0.6 v dd )/t 4 parameter [4] description conditions min typ. max units er rising edge rate output clock edge rate. measured from 20% to 80% of v dd . c load = 15 pf. see figure 7 . 0.75 1.2 ? v/ns ef falling edge rate output clock edge rate. measured from 80% to 20% of v dd . c load = 15pf see figure 7 . 0.75 1.2 ? v/ns t 9 clock jitter period jitter ? 250 ? ps t 10 pll lock time ? 1 5 ms f xo vcxo crystal pull range using non- smd-49 crystal specified in ?cy22388 appli- cation note, anc0002? nominal crystal frequency input assumed (0 ppm)at 25c and 3.3v 110 120 ? ppm using smd-49 crystal specified in ?cy22388 application note, anc0002? nominal crystal frequency input assumed (0 ppm)at 25c and 3.3v 105 120 ? ppm ac parameters (continued) dut v dds outputs c load gnd 0.1 f t 2 t 1 clock output 0v v dd 50% of v dd t 3 t 4 80% of v dd 20% of v dd clock output v dd 0v [+] feedback
cy22388, cy22 389, cy22391 document #: 38-07734 rev. *c page 7 of 10 figure 8. fs controlled clock output package drawing and dimensions figure 9. 16-pin tsso p 4.40 mm body zz16 start at full cycle finish cycle t wait fs note 6. the cy22388zxc-xxx, cy22389zxc-xxx, and cy2 2391lfxc-xxx are factory programmed configurations. for more details, contact your local cypress fae or cypress sales representative. 7. not recommended for new designs. the ly32 qfn package transitions to the lt32 qfn. ordering information part number [6] package type production flow pb-free cy22388zxc-xxx zz16 16-pin tssop commercial, 0c to +70c CY22388ZXC-XXXT zz16 16-pin tssop - tape and reel commercial, 0c to +70c cy22389zxc-xxx zz20 20-pin tssop commercial, 0c to +70c cy22389zxc-xxxt zz20 20-pin tssop - tape and reel commercial, 0c to +70c cy22391lfxc-xxx [7] ly32 32-pin qfn (punch) commercial, 0c to +70c cy22391lfxc-xxxt [7] ly32 32-pin qfn (punch) - tape and reel commercial, 0c to +70c cy22391ltxc-xxx lt32 32-pin qfn (saw) commercial, 0c to +70c cy22391ltxc-xxxt lt32 32-pin qfn (saw) - tape and reel commercial, 0c to +70c 4.90[0.193] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 16 pin1id 6.50[0.256] seating plane 1 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] bsc. 5.10[0.200] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] bsc 0.25[0.010] 0-8 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] plane gauge dimensions in mm[inches] min. max. reference jedec mo-153 package weight 0.05 gms part # z16.173 standard pkg. zz16.173 lead free pkg. 51-85091-a [+] feedback
cy22388, cy22 389, cy22391 document #: 38-07734 rev. *c page 8 of 10 figure 10. 20-pin thin shrunk small outline package (4.40-mm body) zz20 figure 11. 32-pin punch qfn (5 x 5 mm) ly32 20 pin1id seating plane 1 bsc. bsc 0-8 plane gauge 6.40[0.252] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 6.50[0.256] 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] 6.60[0.260] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] 0.25[0.010] 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] dimensions in mm[inches] min. max. reference jedec mo-153 part # z20.173 standard pkg. zz20.173 lead free pkg. 51-85118-a 51-85188-b [+] feedback
cy22388, cy22 389, cy22391 document #: 38-07734 rev. *c page 9 of 10 figure 12. 32-pin sawn qfn (5 x 5 mm) lt32 001-30999 *a [+] feedback
document #: 38-07734 rev. *c revised january 13, 2009 page 10 of 10 all products and company names mentioned in this document may be the trademarks of their respective holders. cy22388, cy22 389, cy22391 ? cypress semiconductor corporation, 2005-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy22388, cy22389, cy22391 factory programmable quad pll clock generator with vcxo document number: 38-07734 rev. ecn orig. of change submission date description of change ** 320458 rgl 03/07/05 new data sheet internal setting in vcxo are:xob/a=110, offset=1110, gain=101 *a 389649 rgl 08/02/05 changed r1 value to max. 40 changed dl comments and max. value to 300 w changed f xo min. value to 110ppm and typ. value to 120ppm *b 523597 rgl 11/12/06 specified a non-smd-49 and smd-49 crystal specs in the vcxo pull range parameter *c 2632357 kvm 01/13/09 updated template. updated ordering information table to add tape & reel part numbers. added lt32 (saw) qfn package for cy22391, including package drawing. ly32 (punch) qfn package ?not recommended for new designs? added package column to ordering information table and cleaned up package references in captions of the package drawings. changed document title to spell out each part number in full. clarified that power down (pd#) is active-low: in block diagram, cy22389 pinout and in pin description table. replaced pdwn and pd with pd#. changed package diagram 51-85188*a to 51-85188*b. [+] feedback
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